Capacitor sample and hold circuit employing singal comparison and regeneration



June 25, 1968 H JR 3,390,381

CAPACITOR SAMPLE AND HOLD CIRCUIT EMPLOYING SIGNAL COMPARISON ANDREGENERATION Original Filed May 19, 1960 3 Sheets-Sheet 1 BY M, 4m ,m W

F. H. SHEPARD. JR CAPACITOR SAMPLE AND HOLD CIRCUIT EMPLOYING SIGNALCOMPARISON AND REGENERATION 3 Sheets-Sheet 2 June 25, 1968 OriginalFiled May l9. 1960 June 1968 F. H. SHEPARD. JR

CAPACITOR SAMPLE AND HOLD CIRCUIT EMPLOYING SIGNAL COMPARISON ANDREGENERATION Original Filed May 19, 1960 5 Sheets Sheet 3 United StatesPatent ABSTRACT OF THE DISCLOSURE Electronic memory system in which adigit (e.g. any decimal digit) is represented by a corresponding voltagelevel on a capacitor, the voltage being periodically regenerated toprovide for long-term accuracy. Regeneration is accomplished at a ratefast enough to prevent any effective change of the voltage stored on thecapacitor,

. and accuracy is obtained by resetting the capacitor voltage to anexact level corresponding to whatever level should then be stored on thecapacitor. Change from one digit to any other within the range of thesystem is electronically controlled in accordance with an input signal.

This application is a continuation-in-part of copending application Ser.No. 641,653 filed Feb. 21, 1957, now United States Patent 2,947,910, anda division of copending application Ser. No. 30,216 filed May 19, 1960,now United States Patent 3,273,013.

This invention relates to an improved technique and apparatus foridentifying and remembering a number, more particularly it relates to anelectronic memory and system for representing a long series of numbersof characters in electrical form and for remembering and easilyidentifying any chosen number of the series.

An object of this invention is to provide a high speed memory which hasthe relative simplicity and tremendous range of an electric voltagecapacitor memory, but with effectively the permanence orinformationretaining ability of a magnetic core memory.

Another object is to provide a system of counting which is compatiblewith practical electrical circuits.

Still another object is to provide a numbering and memory system whichcan be built inexpensively and compactly and which will operate with anextremely high degree of reliability.

These and other objects will in part be pointed out in and in partunderstood from the description of the invention given hereinafter.

There are many applications where to obtain high speed operation it isnecessary to represent a series of numbers in terms of electricalimpulses. Thus, in a high speed printer, such as shown in the inventorsUS. Patent No. 2,787,210, information, for example in the form of binarydigits, is read oil. of a magnetic tape and typed out on paper at therate of about 40,000 words per minute. This compares with a typing speedof about 70 words per minute for a good secretary. In this printer, 64alphanumeric characters, corresponding to the keyboard characters of anordinary oilice typewriter, are arranged around each of 190closely-spaced circular type-wheels. These are rotated in unison at highspeed and paper to be printed on is moved stepwise tangentially beneaththem. During each step-by-step pause of the paper, a row of 190 hammersbeneath the paper and wheels are selectively fired upward and drive thepaper against an 3,390,381 Patented June 25, 1968 ice inked ribbon andany chosen print character on each Wheel to print an entire line ofwords across the paper. Now, it takes at least one revolution of theprint wheels for every one of the 64 characters on each wheel to rotateopposite the type hammers. Moreover, each hammer must be actuated at theprecise instant (within a few microseconds) that the desired charactermoves opposite it. This then requires a highly accurate way of countingthe characters to identify them as they rotate past the hammers.Furthermore, because it takes a finite time, i.e. one revolution of thetype wheel, for all 64 characters to pass a hammer, it is necessary toremember, at least for this long, what character is to be printed untilthis particular character is in printing position. Thus, for each of thehammers and type wheels it is necessary to provide a high speed way ofcounting or numbering the positions of the type characters, and ofremembering the characters to be printed after they have been read fromthe tape and until they have actually been printed. The presentinvention provides a highly successful and advantageous system for doingthis.

One previously known type of memory uses an array of small saturablemagnetic cores or toroids in which information in the form of binarynumbers is stored according to whether each core is magnetized in onedirection or the other. Because the information is stored as arelatively permanent magnetic flux, a memory device of this kind iseffectively perfect in its ability to remember any given numberindefinitely and until told to remember a different one. Unfortunately,because a magnetic core normally has only one of two states, that is,magnetized in one direction or the other, to be able to remember a largenumber, eg a number as large as 64, a great number of individual coresmust be used in a rather intricate array. This is a serious drawbackfrom the standpoint of cost where a multitude of large number seriesmust be remembered.

A second kind of memory generally known before uses simply a capacitorin which an electrical charge corresponding to a number can be stored.Here, the number which can be remembered can be any one of a largeplurality of them depending upon the sensitivity and resolving abilityof associated equipment used to read the memory. Thus, for example, itis an easy matter with inexpensive, existing equipment to charge acapacitor with a voltage corresponding to any digit from 0 to 10 andthereafter accurately read the voltage to determine the number.Unfortunately, this kind of memory tends to forget the informationstored in it since the electrical charge on a capacitor leaks oil? intime. This has been so serious a defect that until now capacitormemories have had only very limited practical use. The present inventioneliminates this difficulty and makes possible a capacitor memory havingwide range, extreme reliability and remembering ability, and low cost.

In accordance with one aspect of the present invention, a series ofnumbers is represented as a voltage which increases step-by-step like astaircase, each step representing a separate and distinct number. Now,for practical considerations such as the ability of associated equipmentto distinguish between voltage levels, and for high reliability it isdesirable to provide a rise of several volts or so for each level of thestaircase. Thus, in a memory system for use with the above describedhigh speed printer having 64 characters around the type wheels, twovoltage staircases are used. Each staircase has eight levels, the firstor fine staircase having a rise or step corresponding to each character,the other or coarse staircase having a respective step corresponding toeach successive group of eight characters. By determining first theparticular level or step of the coarse staircase, and then the level ofthe fine, any one of the 64 characters to be printed can be chosen. Ifthere were 100 characters, then a coarse and a fine staircase of 10steps each could be used and counting would be analogous to conventionaldecimal arithmetic.

In accordance with a principal aspect of the invention, a number isremembered by charging a capacitor to a corresponding voltage level.Then, by comparing this remembered voltage to a voltage staircaserepresenting a series of numbers, for example one to eight, acoincidence pulse marking the instant the staircase voltage equals theremembered voltage is obtained. This pulse, which identifies the numberbeing remembered, in turn is used to actuate momentarily a uniqueelectronic switch provided as part of the system to apply to the memorycapacitor a voltage derived from the staircase voltage and equal to thevoltage which should be remembered. In this way the remembered voltageon the capacitor is continuously regenerated. Thus the ditficulty withprevious capacitor memories of gradually losing the information storedis eliminated. This new memory can retain the information read into itindefinitely, but, as will be explained in detail later on, can be resetto remember a new number almost instantaneously. Readout of informationis easily accomplished without losing the information stored. A singlecapacitor memory can easily remember any of 10 different numbers andthis is of far reaching importance in the field of electronic computing.

A better understanding of the invention together with a fullerappreciation of its many advantages will best be gained from thefollowing description given in connection with the accompanying drawingswherein:

FIGURE 1 illustrates a method of counting according to the invention;line a representing a repetitive sequence of 64 pulses evenly spaced intime; each corresponding to a number from 1 to 64 as indicated, line bshowing a series of fine staircase waveforms having vertical steps orrisers on the occurrence of each pulse in line a up to eight, thenrepeating for the next eight and so on; and line showing a coarsestaircase having a step for each group of eight pulses, and so on.

FIGURE 2 shows a capacitor memory system embodying features of theinvention; and

FIGURE 3 shows a fine staircase voltage generator used with the systemshown in FIGURE 2.

Line a of FIGURE 1 represents by short vertical lines P, which inpractice are narrow voltage pulses, a sequence of 64 numbers. Assumingthat these correspond to the print characters in the above describedhigh speed printer, the entire sequence will be repeated upon eachrevolution of the print wheels. Each pulse in the sequence of line aidentifies in time a particular character on a print wheel, and thecharacters or numbers are evenly spaced in time. Knowing at what instanta particular number occurs (by counting and remembering as describedbelow) it is then possible to actuate a type hammer and print thecorresponding character.

Line b of FIGURE 1 shows a fine staircase voltage waveform having avertical riser R at the instant of occurrence of each pulse P in line aand having a horizontal level L for the time between pulses. The firstwaveform W represents eight pulses, namely, 0 to 7. Approximately midwaybetween numbers 7 and 8 the waveform returns or is knocked down asindicated at K to zero level and then at number 8 a second waveform Wrepeats, and so on.

Line 0 of FIGURE 1 shows a coarse staircase voltage waveform Y having avertical riser Q occurring just before every eighth pulse P up to 64,and then repeating in a second waveform Y, etc. This coarse staircase Yis generated synchronously with the fine staircase W, each knockdown Kserving as a timing pulse to initiate as a suitable delay each riser Qof the coarse staircase. The latter has a corresponding step or level Sto identify each octal group in line a, fine staircase W serving toidentify each pulse in each octal group. Thus, for example, pulse number11 will occur during the second step of the coarse staircase and exactlyat the fourth riser of the fine staircase. In this way, by rememberingthe particular levels of the coarse and fine staircases, any one of the64 numbers is identified in time.

FIGURE 2 is a schematic diagram of an electronic memory circuit providedaccording to the invention. Near the left center of the drawing is showna fine memory capacitor 102 which is adapted to be charged to a levelcorresponding (but differing by a fixed amount) to a level L of a finestaircase W in line b in FIG- URE 1. This capacitor need not be large orspecially made, it should however be free of hysteresis. A .1000micromicro-farad (1000 mmf.) Mylar tubular capacitor has been found verysatisfactory in this particular circuit.

Capacitor 102 is adapted to be charged to a desired level through adecoupling diode 104 from the cathode of a buffer tube 105. The grid ofthis tube is connected through a de-coupling diode 108 to a fine levelinput lead 110 to which is applied the desired voltage level. Thisvoltage is derived, for example, from binary digits recorded on amagnetic tape, these digits being read from the tape and then translatedin a suitable decoder circuit (not shown, but known in the art) to avoltage of given level. How ever, as will be explained later, beforethis voltage can be applied to memory capacitor 102, tube 106 must beunblocked, this being accomplished by unclamping its grid. The grid oftube 106 is normally biased to cut off by means of a diode 112 whosecathode is connected to the plate of a gating tube 114 and a load pulseinput tube 116. When either of the latter is conducting, the grid oftube 106 is held suificiently negative so that it cannot conduct. Whenboth are oil, the DC. level on lead 110 is applied through tube 106 anddiode 104 to memory capacitor 102. To insure that the proper D.C. levelis transmitted through tube 106, its cathode is biased to C by a loadresistor 118 and it is also clamped to B by a diode 120. Tube 106 needonly be energized briefly (tube 114 being gated open and tube 116 beingmomentarily pulsed off) to charge memory capacitor 102 to a desiredlevel, thereafter the tube is turned off and the capacitor is held atthis voltage (for as long as desired, as will be explained) untilanother voltage is fed in through tube 106.

On the right in FIGURE 2 is a coarse memory capacitor 122 which isadapted to remember a voltage corresponding (but differing by a fixedamount) to a level S of a coarse staircase Y in line c of FIGURE 2. Thiscapacitor, which is identical to fine memory capacitor 102, is connectedvia a lead 124 through a de-coupling diode 126 to the cathode of abutter tube 128. This tube is connected and operated the same way asbuffer tube 106, the grid of tube 128 being connected through a diode130 to a coarse level input lead 132. This grid of tube 128 is normallybiased off by a diode 134 whose cathode is connected in common with thecathode of diode 112 to the plates of tubes 114 and 116. The cathode ofbuffer tube 128 is connected through a resistor 136 to C and is clampedby a diode 138 connected to -13.

Assuming that the desired voltage levels to be applied to the memorycapacitors 102 and 122 exist respectively on leads 110 and 132, and thattube 114 has previously been placed in open gate condition, then amomentary negative pulse applied to tube 116 will cause both memorycapacitors to be loaded to the desired levels, respectively. As soon asthe loading pulse applied to tube 116 disappears, the tube againconduct-s and blocks both buffer tubes 106 and 128 thereby disconnectingthem, though the action of diodes 104 and 126, from their respectivememory capacitors.

Fine memory capacitor is connected via the grid of a cathode followertube 140 to the cathode of a fine level coincidence tube 142, the commoncathodes of these tubes being connected to a load resistor 144 and C.The grid of coincidence tube 142 is connected to a lead 146 to which isapplied a fine staircase voltage W, cyclically repeated, as illustratedby line b of FIGURE 1. Whenever this voltage rises above the voltagelevel then at memory capacitor 102, a negative pulse appears at theplate of tube 142 across its load resistor 148. This negative pulse iscoupled through a small capacitor 150 and a decoupling resistor 152 tothe grid of a tube 154. This latter tube is normally biased on through agrid resistor 156 connected to +13. The tube is connected in parallelwith a similar tube 160, also normally on and which, as will appear, isgated off by the coarse staircase waveform Y in conjunction with coarsememory capacitor 122.

To determine precisely the timing of the negative pulse appearing at theplate of tube 142, the voltage on fine memory capacitor 102 is setapproximately midway between two successive voltage levels L of waveformW. Thus precisely at the riser R between these levels, the finestaircase voltage W will become greater than the voltage of fine memorycapacitor 102, and thereupon, as explained above, a negative pulse willappear at the plate of tube 142 and momentarily turn tube 154 off. Now,

' when tube 160 is at the same time also 011, a positive voltage pulsewill appear at the plates of these tubes across their load resistor 162.A small RF (radio frequency) capacitor 164 bypasses this resistor toground. Unless tube 160 is off, there effectively cannot be a positivevoltage pulse at the plate of the tube and tube 154.

The grid of tube 160 is normally positive and is coupled through aresistor 166 and a capacitor 168 to the plate of a tube 170, a loadresistor 172 connecting this plate to I-B. The grid of the latter tubereceives via a lead 174 the coarse staircase voltage waveform Y. Tube170 operates in conjunction with a tube 176, these tubes having a commoncathode resistor 178 connected to C. When the coarse staircase Y exceedsthe voltage set on coarse memory capacitor 122, a negative voltageappears at the plate of tube 170. This voltage has a durationapproximately equal to the duration of the remaining coarse staircase (ie. until the resetting of the coarse staircase level K on the coarsestaircase in FIGURE 1) and is applied to the grid of tube 160 to turn itoff during one coarse level during this interval. At the knockdown K ofthe fine staircase W corresponding to the particular coarse staircaselevel S in question, a positive voltage pulse is applied to the grid oftube 160 through a cold gas diode 180 via a lead 182. This puts avoltage charge on capacitor 168 and holds tube 160 on through the end ofthe present coarse staircase waveform Y and until the interval in thenext waveform Y when the coarse staircase voltage again rises above thelevel set on coarse memory capacitor 122. Because the risers Q of voarsestaircase waveform Y occur just slightly before the corresponding risersR of fine staircase waveforms W, tube 160 will, at the selected eightpulse interval, be turned off for a time long enough to encompass alleight risers R of the thus selected waveform W. As with the voltage seton the fine memory capacitor, the voltage set on coarse memory capacitor122 is set at a value between two successive steps S of waveform Y. Thusthe point at which a coarse staircase Y exceeds the voltage set oncoarse memory capacitor 122 is marked by a riser Q of the coarsestaircase.

The positive voltage pulse appearing at the plates of tubes 154 and 160when there is a dual coincidence between the fine and coarse staircasevoltages respectively, and the corresponding voltages set on the fineand coarse memory capacitors, is applied via a lead 184 and a couplingcapacitor 186 to an RF generator indicated at 190. The momentary voltageapplied to the input of the generator produces a momentary but somewhatlonger burst of RF voltage, as indicated by the waveform at the right ofthe generator, which dies exponentially, rather than suddenly, to zero.

This burst of RF voltage is used to control a unique switch, now to bedescribed. One such switch is indicated,

to the right of generator 190, at 192. This comprises a gas diode 194,such as a neon NE-Z, having two electrodes 196 and 198 in a gas filledenvelope 200. Surrounding this envelope is a conductive tubular sleeve202. The latter is connected to the output lead 204 (RFl) of generator190.

When the RF voltage burst described above appears on shield 202, the gasinside tube 194 is ionized and the tube becomes a good conductor, hencea closed switch. When the RF voltage dies out the gas de-ionizes(assuming the potential across electrodes 196 and 198 is less than theglow voltage) and the tube ceases altogether to conduct. It then becomesan open switch. Because the RF voltage is controlled to die outgradually, the tendency of self-rectification of the gas diode iseliminated. This is most important. If the RF voltage were turned offsuddenly, there would on the average be a volt or so drop acrosselectrodes 196 and 198 at the instant of cutoif. Now, where a switch 192is being used to charge a capacitor (such as fine memory capacitor 102)to exactly a given voltage, there cannot be tolerated any voltage dropacross the switch at the instant of turnoff. Accordingly, the use of agradually dying-out RF voltage pulse to actuate such a switch isessential.

The output signal from circuit is obtained at its lower right from alead 210- which is bypassed to ground by a small capacitor 212 and isconnected to one side of a switch 192. When this switch is turned on,there is established a conductive path to a storage capacitor 214. Thelatter is adapted to be charged to a suitable voltage through a gasdiode 216 and thereafter left in charged condition until switch 192 isclosed. An important advan tage of this arrangement is that an outputsignal is obtained only if capacitor 214 has been charged, moreover,this output signal can have a sizeable magnitude at low impedance eventhough the signal actuating RF generator is small. Further, as manyseparate output signal leads as desired can be provided simply byproviding additional elements, as indicated.

The RF lead 204 is also connected to another switch 192 one side ofwhich is connected to fine memory capacitor 102 and the other side ofwhich is connected to a lead 220. The latter is energized with a voltagehaving a waveform identical to fine staircase W 'but suitably shifteddown in DC. level. Thus for a given level L of staircase W, thecorresponding level of the voltage on lead 220 will be approximatelymidway between this level L and the one below or preceding it. Thevoltage on lead 220 is in fact derived from the fine staircase voltageby taking the latter and shifting its absolute or DC. level down by anappropriate fixed amount.

Now when RF lead 204 is energized, the switch 192 in series with finememory capacitor 102 and lead 220 will be closed for a short instant.But the voltage at this instant on lead 220 will be precisely equal tothe voltage which is being remembered by capacitor 102. Accordingly,

even though some of the voltage previously set on capacitor 102 (throughtube 106 or from lead 220) has since leaked off, the voltage will now bere-set from lead 220 to the exact value it should have. Once set to agiven voltage, fine memory capacitor will continue to be reset in thismanner until intentionally set to a different voltage (through tube106).

Simutaneously with the continual regeneration of the voltage on finememory capacitor 102, coarse memory capacitor 122 is re-set to thedesired voltage through a switch 192 and a lead 222. The latter hasapplied to it a voltage derived from the coarse staircase Y but shifteddown in DC. level an appropriate fixed amount.

Near the lower center of FIGURE 2 is a cluster of three switches 192,one side of each being grounded. They are controlled in unison by an RFgenerator 224 similar to generator 190 but independently actuated. Whenturned on, the first of these switches through a lead 226 dischargesfine memory capacitor 102. The second switch grounds lead 124 anddischarges coarse memory capacitor 122.

The third switch through a lead 228 grounds one side of capacitor 168and insures that tube 160 is turned on. Thereafter, when these threeswitches are opened, the fine and coarse memory capacitor can be set towhatever new levels are desired. The setting of new voltages to beremembered can be accomplished very quickly.

RF generator 190 includes an input buffer tube 230 which is connectedvia a pulse stretching network consisting of a resistor 232 and acapacitor 234 to an oscillator tube 236. Network 232, 234 keeps theoscillator turned on for longer than the duration of the pulse appliedto buffer tube 230 and this network also gradually turns the oscillatoroff so that the burst of RF voltage on lead 204 does not die outsuddenly. Tube 236 in conjunction with a high-Q coil 238, a resonantcapacitor 240 and a feedback coil 242 functions as a Hartley typeoscillator. Its output is applied through a coupling capacitor 244 tolead 204. A choke coil 246 grounds lead 204 to DC. In an actual unit theRF pulse applied to lead 204 had an amplitude of about 100 to 200 volts,a frequency of about 2 megacycles, a duration of 30 to 40 microseconds,and a die-out of to microseconds. The interval between pulses P wasabout 800 microseconds and the peak-to-peak amplitude of a waveform W orY, about 70 volts.

FIGURE 3 shows a fine staircase generator 300 which is adapted to supplythe requisite voltages to leads 146 and 220 in FIGURE 2. Also, a pulse Kis derived from generator 300 which after suitable amplification andshaping is applied to lead 182 in FIGURE 2. The operation of circuit 300is for the most part conventional and will be understood by thoseskilled in the art. Accordingly, only a brief description of the circuitwill be given. It is to be understood that a closely similar circuit canbe used to generate the coarse staircase voltages needed in FIGURE 2(leads 174, 222).

Circuit 300 at the left has an input terminal 302 adapted to beenergized by a symmetrical square wave, derived from pulses P in FIGURE1 and having the same repetition rate or frequency. This square Wave isapplied through a capacitor 304 to a pair of clamping diodes 306 and 308to charge a capacitor 310 step-by-step. To the right of the latter isconnected a tube 312 which serves as a cathode follower to keep thecharging of the capacitor linear. The ratio of capacitor 310 tocapacitor 304 determines the amount of each step of waveform W.

To the right of tube 312 is connected a tube 314, which in conjunctionwith a tube 316, a capacitor 318, a clamping diode 320 and an adjustablebattery 322 determine the number of steps in a waveform W.

Also connected to the same potential as the grid of tube 312 through alead 324 is a cathode follower tube 326. This through a resistor 328 isadapted to charge a capacitor 330. The latter when sufficiently chargedraises the potential on the grid of a tube 332 adjustably biased througha battery 334 to cause the knockdown of waveform W as indicated at K inFIGURE 1. Battery 334 can be adjusted to locate knockdown K wheredesired. A tube 336 discharges capacitor 330. To insure that capacitor310 returns to its consistent zero position the cathode of tube 336 isused as a negative clamp or excursion limit for the cathode of 316 and314 which discharges capacitor 310 through the grid-cathode current oftube 312. To insure that capacitor 304 returns to its zero conditionupon knockdown a tube 338 is provided.

One output of circuit 300 is obtained through a gain adjusting resistor340 in the cathode of tube 326. This is coupled via a capacitor 342 to acathode follower tube 344 and a DC. level adjusting diode 346 andbattery 348. Waveform W is obtained at terminal 350. A similar waveformbut shifted in level (for lead 220 in FIGURE 1) is obtained at terminal352 from an identical arrangement.

It is to be understood that a single generator 300 can supply a numberof memory circuits 100. Also, where a smaller capacity memory isdesired, the coarse staircase portion, for example, of circuit can bedispensed with. The above description of the invention is intended inillustration and not in limitation. Various changes or modifications inthe embodiment set forth may occur to those skilled in the art and canbe made without departing from the spirit or scope of the invention asset forth.

I claim:

1. A memory system comprising a capacitor adapted to be charged to avoltage to be remembered, coincidence means to compare said voltage witha changing voltage, and reset means responsive to said coincidence meansto periodically recharge said capacitor to said voltage to beremembered, and in further combination with means for generating astaircase voltage from-a train of pulses, said capacitor holding aparticular voltage corresponding to a point on said staircase, saidcoincidence means determining when said staircase voltage crosses saidcapacitor voltage, and signal output means responsive to saidcoincidence means to give an output pulse.

2. The system as in claim 1 wherein said re-set means includes switchmeans actuated by said output pulse for applying to said capacitor are-set voltage effectively equal to said particular voltage, wherebysaid particular voltage will be held indefinitely until intentionallychanged to different value.

3. A capacitor memory system comprising a capacitor, means to chargesaid capacitor to a first voltage, coincidence means connected to saidcapacitor, means to apply a staircase voltage to said coincidence means,output signal means responsive to said coincidence means upon theequaling of said staircase voltage and said first voltage, and switchmeans controlled by said output means to recharge said capacitoreffectively to said first voltage.

4. The system as in claim 3 wherein said means to charge said capacitorincludes means to first return said capacitor to zero condition.

5. The system as in claim 3 in further combination with a secondcapacitor adapted to remember a second voltage, said second capacitoralso being connected to said coincidence means, and second means toapply a staircase voltage to said coincidence means whereby only uponthe dual coincidence of said staircase voltages and said first andsecond voltages respectively is an output signal obtained.

6. A system of remembering a voltage comprising, a capacitor, means forcharging said capacitor to a given voltage to be remembered, means forgenerating a voltage changing with time, means for periodicallycomparing said capacitor voltage to said voltage changing with time andupon coincidence of said changing voltage and said capacitor voltage forrecharging said capacitor effectively to the voltage to be remembered.

7. The system in claim 6 wherein said means to generate produces avoltage periodically repeating step-bystep or a first staircase voltage,and produces a second staircase voltage derived from the first staircasevoltage but shifted in DC. level so that its steps lie between the stepsof said first staircase voltage, and said means for comparingimmediately after said first staircase voltage crosses said capacitorvoltage connects said capacitor to a level of said second staircasevoltage whereby said capacitor is continually reset to effectively saidgiven voltage.

References Cited UNITED STATES PATENTS 6/1958 Johnson 328-151 7/1960Deighton 328-151

